Microscopy, X-ray, Mechanical testing, Thermal Analysis
IndustriesMaterials Testing
ManufacturerThermo Fisher Scientific
Importance of the topic
The evolution of semiconductor packaging toward 2.5D/3D integration, fan-out wafer-level packaging and heterogeneous chiplet assemblies has enabled dramatic gains in performance, power efficiency and functional density for AI, 5G, HPC and mobile systems. These architectures, however, introduce complex multi-material stacks and buried interconnects that create new, often subtle failure modes. Robust failure analysis (FA) is therefore essential to identify root causes, improve yield, guarantee field reliability (especially for automotive/aerospace), and accelerate time-to-market for advanced packages.
Objectives and scope of the white paper
This white paper surveys failure mechanisms characteristic of advanced packaging and reviews modern FA tools and workflows. Its aims are to: summarize common failure modes (electromigration, delamination, TSV stress, solder fatigue, warpage), compare non-destructive and destructive FA techniques, present multi-level FA workflows (wafer, die, device), and highlight automation and software that accelerate diagnosis and root-cause analysis.
Methodology and analytical techniques
The review groups methods into non-destructive and destructive approaches and emphasizes multi-modal FA to cover the trade-offs between resolution, penetration depth and throughput.
Non-destructive techniques:
- X-ray computed tomography (XCT): 3D imaging of voids, solder joints, TSVs and underfill. Micro-CT (~1 µm) and nano-CT (<100 nm) provide different resolution–penetration trade-offs; dual-energy XCT aids material differentiation. Limitations include beam hardening artifacts, low contrast for low-Z materials, and challenges imaging ultra-dense logic at sub-5 nm nodes.
- Scanning acoustic microscopy (SAM): Ultrasonic imaging for delamination, voids and bond integrity. Frequency-dependent resolution from ~0.5 µm (UHR-SAM) to tens of microns; better for polymer/adhesive defects and near-surface interrogation but limited in metal-dense regions and deeper buried layers at very high frequencies.
- Lock-in thermography (LIT): Active thermal excitation with phase-sensitive IR detection to find hotspots from electromigration, shorts and resistive defects. Spatial resolution depends on thermal diffusion length and modulation frequency; excels at locating active electrical faults but offers limited structural detail in metal-rich areas.
Destructive / high-resolution techniques:
- DualBeam FIB-SEM: Site-specific milling and cross-section imaging for 3D reconstruction of buried interfaces, combined with EDS/EBSD for elemental and crystallographic information. Excellent for targeted delayering and defect exposure.
- Transmission electron microscopy (TEM / (S)TEM): Atomic-scale imaging and EDS mapping for intermetallic compounds (IMCs), nanoscale voids, crack nuclei and phase identification. 3D TEM tomography and in-situ TEM enable observation of crack propagation and IMC evolution under stress.
Trade-offs and combined approaches:
- No single method covers all needs; XCT provides package-level context, SAM and LIT detect mechanical and thermal faults, while FIB-SEM/TEM deliver nanoscale identification. FA workflows therefore combine techniques to localize, expose and characterize defects.
- The paper highlights resolution vs penetration vs throughput constraints (e.g., nano-CT time cost vs micro-CT throughput), and the particular difficulty of imaging sub-10 nm interconnects in advanced logic.
Instrumentation used
The white paper emphasizes an integrated toolset (many Thermo Scientific systems are used as examples):
- Thermo Scientific ELITE System (wafer-level 3D thermal fault localization and high-throughput inspection)
- Thermo Scientific Apreo ChemiSEM System (high-resolution SEM with rapid elemental analysis)
- Thermo Scientific Helios 5/Helios 5 Hydra PFIB-SEM and Helios 6 HD FIB-SEM (site-specific delayering, 3D FIB-SEM tomography, precision cross-sectioning)
- Thermo Scientific Talos F200S G2 (S)TEM and Spectra (S)TEM (atomic-resolution imaging, tomography and EDS mapping)
- Software and automation: Avizo (3D visualization and data integration), AutoTEM (automated TEM sample prep), iFast (automated FIB-SEM workflows), Hyperion II, Meridian EX, nProber IV and Metrios for probing and metrology
Main results and discussion
Primary failure mechanisms and key observations summarized in the paper:
- Electromigration (EM): High current densities in microbumps, RDLs and hybrid-bond interconnects produce atom migration, void formation and open/short failures; EM accelerates resistance growth and impacts timing and power integrity.
- CTE mismatch, warpage and die cracking: Multi-material stacks produce thermo-mechanical stress during reflow and temperature cycling, causing delamination, substrate/substrate separation, and die cracking—especially in large FOWLP and heterogeneous chiplet assemblies.
- Solder joint fatigue and whisker growth: Thermal cycling and lead-free solders increase risk of fatigue cracks and tin-whisker induced shorts, affecting flip-chip and BGA interconnect reliability.
- TSV-induced stress: TSVs create localized silicon stress that can shift transistor mobility and impact electrical behavior, requiring stress-mitigation design and material choices.
- Underfill voiding and delamination: Voids reduce mechanical support and thermal conduction, leading to hotspots and progressive interconnect degradation.
Metrology challenges and technique-specific insights:
- Table 1 comparison (summarized): LIT is best for thermal hotspots and active defects with lateral resolution ~5–10 µm (can reach sub-µm with optics) but limited structural detail in metal-rich areas; XCT offers 3D imaging and deep penetration (nano-CT <100 nm, micro-CT ~1 µm) but struggles with low-Z contrast and beam-hardening artifacts; SAM excels for polymer/adhesive defects and delamination with frequency-tunable resolution down to sub-micron but limited for deep metal-dense features.
- Effective FA requires combining localization (ELITE/thermal, acoustic, or X-ray), targeted delayering (FIB-SEM), and nanoscale characterization (TEM), supported by automated software to speed throughput and ensure reproducibility.
Benefits and practical applications
Applying a multi-level, multi-modal FA workflow yields practical benefits:
- Faster root-cause identification reduces scrap and accelerates process corrections, improving yield and lowering manufacturing cost.
- Comprehensive FA supports qualification of new materials and bonding methods (e.g., hybrid bonding), enabling deployment of HBM stacks, chiplets and heterogeneous modules for AI/HPC.
- Automated sample preparation and analysis (AutoTEM, iFast) reduce human variability and turnaround time for TEM-level characterization, which is critical during ramp-up to high-volume manufacturing.
- Improved reliability assessment benefits safety-critical markets (automotive, aerospace) by providing evidence-based mitigation strategies (material selection, underfill improvements, solder formulations, stress-relief design).
Future trends and opportunities
Emerging directions and technological opportunities identified in the white paper include:
- AI and machine-learning-driven FA for automated defect detection, prioritization and root-cause correlation across modalities (XCT, SAM, SEM, TEM).
- Higher-throughput, higher-resolution XCT (faster nano-CT) and improved beam-hardening correction methods to better resolve dense logic stacks.
- In-situ and operando FA (thermal/electrical biasing during TEM or SEM/FIB experiments) to observe real-time failure propagation.
- Data fusion and advanced visualization (3D model integration via Avizo) to link package-level anomalies to nanoscale failure features.
- Materials innovation and process controls to mitigate CTE mismatch and TSV stress—plus improved underfill formulations to reduce voiding and delamination.
- Continued development of automated and metrology-integrated workflows to meet HVM demands while retaining nanoscale investigative capability.
Conclusion
Advanced packaging unlocks system-level performance gains but simultaneously creates layered, multi-physics reliability challenges. Effective failure analysis for these platforms demands an integrated, staged approach that combines non-destructive localization (XCT, SAM, LIT), precision delayering (FIB-SEM), and atomic-scale identification (TEM), supported by automation and advanced software for data integration. Adopting multi-modal FA workflows and leveraging AI-driven analytics will be key to sustaining yield, reliability and rapid commercialization of next-generation heterogeneous packages.
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